发明授权
EP1695472B1 CYCLE-EFFICIENT TDM TIMESLOT REMAPPING FOR NETWORK PROCESSING ENGINES
有权
CYCLE高效TDM ZEITSCHLITZNEUZUWEISUNG处理网络引擎
- 专利标题： CYCLE-EFFICIENT TDM TIMESLOT REMAPPING FOR NETWORK PROCESSING ENGINES
- 专利标题（中）： CYCLE高效TDM ZEITSCHLITZNEUZUWEISUNG处理网络引擎
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申请号： EP04811448.2申请日： 2004-11-17
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公开(公告)号： EP1695472B1公开(公告)日： 2008-07-16
- 发明人: BORKOWSKI, Daniel , BORKOWSKI, Nancy
- 申请人： Intel Corporation
- 申请人地址： 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： 2200 Mission College Boulevard Santa Clara, CA 95052 US
- 代理机构： Dunlop, Hugh Christopher
- 优先权： US723804 20031126
- 国际公布： WO2005055480 20050616
- 主分类号： H04J3/16
- IPC分类号： H04J3/16 ; H04L12/56
摘要：
A method and apparatus for remapping channel data are presented. Multiple successive frames carrying data in timeslots are received. The timeslots are assigned to channels so that data for the channels includes interleaved data. The data from the multiple successive frames for each of a predetermined number of the timeslots are aggregated. The aggregated data is mapped, by timeslot, in the order that the data is aggregated, to produce a timeslot-based map. The aggregated data of the timeslot-based map is remapped to produce a channel-based map in which the data for the channels are grouped together by channel in the order that the data were received.
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