发明公开
EP1724930A3 Low power sigma delta modulator 有权
具有低功耗的Σ-Δ调制器

Low power sigma delta modulator
摘要:
A low power analog-to-digital channel includes a decimation filter coupled to a sigma-delta modulator. Various embodiments include a decimation filter including an output and a sigma-delta modulator coupled to the output of the decimation filter, where a clock frequency applied to the decimation filter is approximately an integral multiple of a sampling frequency of the sigma delta modulator. In an embodiment, the sigma-delta modulator includes one or more successive approximation converters. In an embodiment, the sigma delta modulator includes one or more area efficient integrators.
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