A successive approximation register analog-to-digital converter (SAR ADC) having a sample, hold and convert amplifier circuit may be configured for either a single channel SAR ADC or a multiple channel SAR ADC. Switches or metal connection options, e.g., bit configurable or metal mask configurable, respectively, may be used to configure a common capacitor area, a portion of which may be used as a reconfigurable charge-redistribution digital-to-analog converter (CDAC) of the SAR ADC as either a single channel sample, hold and convert 12-bit capacitor configuration or a four channel sample, hold and convert 10-bit capacitor configuration. All other parts of the SAR ADC circuitry may be substantially the same for either configuration, e.g., the resistive digital-to-analog converter (RDAC), successive approximation register (SAR), ADC controller, sample, hold and convert switches, comparator, etc, may be substantially the same for either the single or multiple channel SAR ADC configurations.