An automatic test system of the type having a pattern generator for generating a stimulus pattern to be applied to a device under test and an expect pattern representing expected responses from the device under test, CHARACTERIZED in that the automatic test system includes synchronization circuitry the synchronization circuitry having:
at least one input receiving a stream of data values from a device under test;
a comparator coupled to the at least one input, having an output indicating when a start condition is detected in the stream of data values from the device under test;
a buffer circuit receiving the stream of data values from the device under test and providing an output stream of data values that duplicates a portion stream of data values from the device under test, the portion selected based on the indication of the start condition from the comparator delayed a deterministic amount relative to the stream of data values from the device under test;

wherein the output stream of the buffer circuit is coupled to the pattern generator for determining whether the device under test produced the expected response;
the automatic test system having a failure processor for comparing an expected response from the device under test to the actual response, the automatic test system circuitry being specially adapted to test a plurality of devices under test that respond to the stimulus pattern at independent times, said buffer circuit being arranged for buffering a response signal representing a stream of data values from each of the devices under test; and the buffer circuit being arranged to output a plurality of such streams of data values and applying them to the failure processor, each stream of data values representing a response from one of the devices under test, with all of the streams synchronized at the failure processor based on the time of response to the device under test generating the response signal.