发明授权
- 专利标题: TLB LOCK INDICATOR
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申请号: EP06789946.8申请日: 2006-08-22
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公开(公告)号: EP1934753B1公开(公告)日: 2018-08-08
- 发明人: AUGSBURG, Victor Roberts , DIEFFENDERFER, James Norris , BRIDGES, Jeffrey Todd , SARTORIUS, Thomas Andrew
- 申请人: QUALCOMM Incorporated
- 申请人地址: 5775 Morehouse Drive San Diego, CA 92121 US
- 专利权人: QUALCOMM Incorporated
- 当前专利权人: QUALCOMM Incorporated
- 当前专利权人地址: 5775 Morehouse Drive San Diego, CA 92121 US
- 代理机构: Dunlop, Hugh Christopher
- 优先权: US210526 20050823
- 国际公布: WO2007024937 20070301
- 主分类号: G06F12/1027
- IPC分类号: G06F12/1027 ; G06F12/126 ; G06F12/12 ; G06F12/10
摘要:
A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
公开/授权文献
- EP1934753A1 TLB LOCK INDICATOR 公开/授权日:2008-06-25
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