发明公开
- 专利标题: Memory device, memory controller and memory system
- 专利标题(中): 内存设备,内存控制器和内存系统
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申请号: EP08104804.3申请日: 2007-07-12
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公开(公告)号: EP1993099A2公开(公告)日: 2008-11-19
- 发明人: Sato, Takahiko c/o Fujitsu Limited , Uchida, Toshiya c/o Fujitsu Limited , Kanda, Tatsuya c/o Fujitsu Limited , Miyamoto, Tetsuo c/o Fujitsu Limited , Shirakawa, Satoru c/o Fujitsu Limited , Yamamoto, Yoshinobu c/o Fujitsu Limited , Otsuka, Tatsushi c/o Fujitsu Limited , Takahashi, Hidenaga c/o Fujitsu Limited , Kurita, Masanori c/o Fujitsu Limited , Kamata, Shinnosuke c/o Fujitsu Limited , Sato, Ayako c/o Fujitsu Limited
- 申请人: Fujitsu Limited
- 申请人地址: 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 专利权人: Fujitsu Limited
- 当前专利权人: Fujitsu Limited
- 当前专利权人地址: 1-1, Kamikodanaka 4-chome Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 代理机构: Stebbing, Timothy Charles
- 优先权: JP2006345415 20061222
- 主分类号: G11C11/408
- IPC分类号: G11C11/408
摘要:
An image memory, image memory system, memory controller and semiconductor integrated circuit that are capable of efficiently accessing a rectangular area of two-dimensionally arrayed data are provided. The semiconductor integrated circuit in which circuits are integrated on a single semiconductor substrate, the semiconductor integrated circuit comprising: a memory array (224) in which memory cells connected to word lines and bit lines and storing data are arranged in the form of a matrix, and which is sectioned into bit groups for each of Nb number of memory cells; and a controller that selects a bit group as a starting point, on the basis of the address signal and first combination information, the controller outputting, to Nb x N number of output terminals (DQ) in parallel, on the basis of second combination information, data items that are stored in the respective memory cells contained in N number of bit groups including the bit group as the starting point.
公开/授权文献
- EP1993099B1 Memory device, memory controller and memory system 公开/授权日:2010-09-15
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