发明授权
- 专利标题: INSULATED GATE-TYPE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
- 专利标题(中): 绝缘栅型半导体器件及其制造方法
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申请号: EP07707920.0申请日: 2007-01-26
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公开(公告)号: EP1994566B1公开(公告)日: 2018-01-17
- 发明人: TAKAYA, Hidefumi , HAMADA, Kimimori , MIYAGI, Kyosuke
- 申请人: TOYOTA JIDOSHA KABUSHIKI KAISHA
- 申请人地址: 1, Toyota-cho, Toyota-shi, Aichi-ken, 471-8571 JP
- 专利权人: TOYOTA JIDOSHA KABUSHIKI KAISHA
- 当前专利权人: TOYOTA JIDOSHA KABUSHIKI KAISHA
- 当前专利权人地址: 1, Toyota-cho, Toyota-shi, Aichi-ken, 471-8571 JP
- 代理机构: Kuhnen & Wacker
- 优先权: JP2006062602 20060308
- 国际公布: WO2007105384 20070920
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/336 ; H01L29/06 ; H01L29/08 ; H01L29/423 ; H01L21/265
摘要:
A semiconductor 100 has a P− body region and an N− drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P− body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P−− diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P− body region and the P diffusion region, is formed. The P−− diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P−− diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.
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