发明公开
EP2053751A1 INSPECTION MATRIX GENERATION METHOD, ENCODING METHOD, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND ENCODER
审中-公开
检查矩阵生成方法,编码方法,通信装置,通信系统和CODER
- 专利标题: INSPECTION MATRIX GENERATION METHOD, ENCODING METHOD, COMMUNICATION DEVICE, COMMUNICATION SYSTEM, AND ENCODER
- 专利标题(中): 检查矩阵生成方法,编码方法,通信装置,通信系统和CODER
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申请号: EP07791869.6申请日: 2007-08-02
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公开(公告)号: EP2053751A1公开(公告)日: 2009-04-29
- 发明人: MATSUMOTO, Wataru , SAKAI, Rui , YOSHIDA, Hideo
- 申请人: Mitsubishi Electric Corporation
- 申请人地址: 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 JP
- 专利权人: Mitsubishi Electric Corporation
- 当前专利权人: Mitsubishi Electric Corporation
- 当前专利权人地址: 7-3, Marunouchi 2-chome Chiyoda-ku Tokyo 100-8310 JP
- 代理机构: Pfenning, Meinig & Partner GbR
- 优先权: JP2006213722 20060804
- 国际公布: WO2008016117 20080207
- 主分类号: H03M13/19
- IPC分类号: H03M13/19
摘要:
A check-matrix generating method includes a quasi-cyclic matrix generating step of generating a regular quasi-cyclic matrix in which cyclic permutation matrices are arranged in a row direction and a column direction and specific regularity is given to the cyclic permutation matrices; a mask-matrix generating step of generating a mask matrix capable of supporting a plurality of encoding rates, for making the regular quasi-cyclic matrix into irregular; a masking step of converting a specific cyclic permutation matrix in the regular quasi-cyclic matrix into a zero-matrix using a mask matrix corresponding to a specific encoding rate to generate an irregular masking quasi-cyclic matrix; and a check-matrix generating step of generating an irregular parity check matrix with an LDGM (low-density generation matrix) structure in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
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