The present application comprises an integrated circuit comprising a differential input buffer (791) having a first input coupled to a first pad (710,1210) and a second input coupled to a second pad (720,1220); a first single-ended input buffer (751) having an input coupled to the first pad (720,1220); a second single-ended input buffer (756) having an input coupled to the second pad (720,1220);a first single-ended output buffer (771) having an output coupled to the first pad (710,1210); a second single-ended output buffer (776) having an output coupled to the second pad (720,1220); a serial-to-parallel converter (725) having an input coupled to an output of the differential input buffer (791); and a parallel-to-serial converter (715) having an output coupled to an input of the first single-ended output buffer (771).
The present application further comprises a method of providing and receiving signals.