发明公开
EP2381636A1 Transmitting apparatus with bit arrangement method 有权
Sendegerätmit Bitanordnungsverfahren

  • 专利标题: Transmitting apparatus with bit arrangement method
  • 专利标题(中): Sendegerätmit Bitanordnungsverfahren
  • 申请号: EP10184588.1
    申请日: 2004-10-15
  • 公开(公告)号: EP2381636A1
    公开(公告)日: 2011-10-26
  • 发明人: Yano, TetsuyaObuchi, KazuhisaMiyazaki, Shunji
  • 申请人: FUJITSU LIMITED
  • 申请人地址: 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
  • 专利权人: FUJITSU LIMITED
  • 当前专利权人: FUJITSU LIMITED
  • 当前专利权人地址: 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
  • 代理机构: Wilding, Frances Ward
  • 优先权: JP2004035768 20040212
  • 主分类号: H04L27/34
  • IPC分类号: H04L27/34
Transmitting apparatus with bit arrangement method
摘要:
A transmitting apparatus comprising circuitry operable to generate a plurality of bit sequences using bits included in a first data block and a second data block, circuitry operable to control the plurality of bit sequences to correspond to a signal point on the phase plane, comprising a bit sequence generating unit operable to control the generation of the bit sequences to adjust an occupation rate occupied with predetermined bits included in the first data block (CODE BLOCK 1) to be closer to an occupation rate occupied with predetermined bits included in the second data block (CODE BLOCK 2) in regard to bit positions of the predetermined bits, based on an error tolerance of the respective bit sequences generated resulting from the correspondence to a signal point on the phase plane, and circuitry operable to transmit the signals obtained by multi-level modulations in accordance with each signal point.
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