发明公开
- 专利标题: Error control apparatus
- 专利标题(中): Fehlersteuerungsvorrichtung
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申请号: EP11178185.2申请日: 2003-03-20
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公开(公告)号: EP2408136A2公开(公告)日: 2012-01-18
- 发明人: Yano, Tetsuya , Obuchi, Kazuhisa
- 申请人: FUJITSU LIMITED
- 申请人地址: 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: 1-1, Kamikodanaka 4-chome, Nakahara-ku Kawasaki-shi, Kanagawa 211-8588 JP
- 代理机构: Stebbing, Timothy Charles
- 主分类号: H04L1/16
- IPC分类号: H04L1/16 ; H03M13/45 ; H04L1/18
摘要:
In an error control apparatus on a receiving side using a hybrid ARQ which combines an error correcting encoding method and an automatic repeat request method, a buffer stores hard decision result data or soft output data instead of soft decision information in order to reduce a memory capacity of the buffer, and re-encodes the data stored to be provided to a combiner. Alternatively, the number of bits of the data stored in the buffer is restricted or a memory included in a decoder is used as an HARQ buffer.
公开/授权文献
- EP2408136A3 Error control apparatus 公开/授权日:2012-09-05
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