发明公开
EP2524273A1 DYNAMIC LOW POWER MODE IMPLEMENTATION FOR COMPUTING DEVICES
有权
DYNAMISCHE实施者EINES NIEDRIGLEISTUNGSMODUSFÜRBERECHNUNGSVORRICHTUNGEN
- 专利标题: DYNAMIC LOW POWER MODE IMPLEMENTATION FOR COMPUTING DEVICES
- 专利标题(中): DYNAMISCHE实施者EINES NIEDRIGLEISTUNGSMODUSFÜRBERECHNUNGSVORRICHTUNGEN
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申请号: EP11700483.8申请日: 2011-01-10
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公开(公告)号: EP2524273A1公开(公告)日: 2012-11-21
- 发明人: GARGASH, Norman S. , FRANTZ, Andrew J. , SALSBERY, Brian J. , BARRETT, Christopher A.
- 申请人: Qualcomm Incorporated
- 申请人地址: Attn: International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 专利权人: Qualcomm Incorporated
- 当前专利权人: Qualcomm Incorporated
- 当前专利权人地址: Attn: International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 代理机构: Harte, Seán Paul
- 优先权: US965008 20101210; US294055P 20100111
- 国际公布: WO2011085330 20110714
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F1/20
摘要:
The aspects enable a computing device or microprocessor to determine a low power mode that provides the most system power savings by placing selected resources in a low power mode while continuing to function reliably, depending upon the resources not in use, acceptable system latencies, dynamic operating conditions (e.g., temperature), expected idle time, and the unique electrical characteristics of the particular device. Aspects provide a mechanism for determining an optimal low power configuration made up of a set of low power modes for the various resources within the computing device by determining which low power modes are valid at the time the processor enters an idle state, ranking the valid low power modes by expected power savings given the current device conditions, determining which valid low power mode provides the greatest power savings while meeting the latency requirements, and selecting a particular low power mode for each resource to enter.
公开/授权文献
- EP2524273B1 DYNAMIC LOW POWER MODE IMPLEMENTATION FOR COMPUTING DEVICES 公开/授权日:2017-08-23
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