发明公开
EP2616828A1 INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES
有权
损失降低功耗的集成化的电路改进的门控Q-SCAN技术
- 专利标题： INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES
- 专利标题（中）： 损失降低功耗的集成化的电路改进的门控Q-SCAN技术
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申请号： EP11763821.3申请日： 2011-09-15
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公开(公告)号： EP2616828A1公开(公告)日： 2013-07-24
- 发明人: SETHURAM, Rajamani , ARABI, Karim
- 申请人： Qualcomm Incorporated
- 申请人地址： International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 专利权人： Qualcomm Incorporated
- 当前专利权人： Qualcomm Incorporated
- 当前专利权人地址： International IP Administration 5775 Morehouse Drive San Diego, CA 92121 US
- 代理机构： Dunlop, Hugh Christopher
- 优先权： US884482 20100917
- 国际公布： WO2012037338 20120322
- 主分类号： G01R31/3183
- IPC分类号： G01R31/3183 ; G01R31/3185
摘要：
Specific logic gates for q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
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