发明公开
EP2630661A2 TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS
有权
具有改进的连接结构的高压应用TRENCH DMOS器件
- 专利标题: TRENCH DMOS DEVICE WITH IMPROVED TERMINATION STRUCTURE FOR HIGH VOLTAGE APPLICATIONS
- 专利标题(中): 具有改进的连接结构的高压应用TRENCH DMOS器件
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申请号: EP11835123.8申请日: 2011-10-20
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公开(公告)号: EP2630661A2公开(公告)日: 2013-08-28
- 发明人: HSU, Chih-Wei , UDREA, Florin , LIN, Yih-Yin
- 申请人: Vishay General Semiconductor LLC
- 申请人地址: 100 Motor Parkway Suite 135 Hauppauge, NY 11788 US
- 专利权人: Vishay General Semiconductor LLC
- 当前专利权人: Vishay General Semiconductor LLC
- 当前专利权人地址: 100 Motor Parkway Suite 135 Hauppauge, NY 11788 US
- 代理机构: Engel, Christoph Klaus
- 优先权: US909033 20101021
- 国际公布: WO2012054686 20120426
- 主分类号: H01L29/78
- IPC分类号: H01L29/78 ; H01L21/336
摘要:
A termination structure for a power transistor includes a semiconductor substrate having an active region and a termination region. The substrate has a first type of conductivity. A termination trench is located in the termination region and extends from a boundary of the active region to within a certain distance of an edge of the semiconductor substrate. A doped region has a second type of conductivity disposed in the substrate below the termination trench. A MOS gate is formed on a sidewall adjacent the boundary. The doped region extends from below a portion of the MOS gate spaced apart from the boundary toward a remote sidewall of the termination trench. A termination structure oxide layer is formed on the termination trench and covers a portion of the MOS gate and extends toward the edge of the substrate. A first conductive layer is formed on a backside surface of the semiconductor substrate. A second conductive layer is formed atop the active region, an exposed portion of the MOS gate, and extends to cover at least a portion of the termination structure oxide layer.
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