A receiving-side chip is disclosed according to the present invention, which includes a processor, configured to acquire and execute following instructions: receiving link information sent by a sending-side chip, and enabling, according to the link information, a SerDes link to be added; receiving padding data from the added SerDes link according to a short unit frame period to acquire a synchronization word, and determining, according to the synchronization word, whether the added SerDes link has been synchronized; switching a read period of data in the added SerDes link from the short unit frame period into a long unit frame period, and aligning the data of the added SerDes link with the data of an original SerDes link; and receiving service data over the added SerDes link and the original SerDes link.