Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology (130), a master device (105) is connected to a plurality of slaves (S1-S3) communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave (SI -S3) receives data from the master (105) and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can "fill-in" the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock. By adjusting the denominator, the sampling clock can be tuned to match the baud rate of the asynchronous serial data stream received from the transmitting device. Embodiments described include power management, data acquisition (DAQ), etc.