The disclosed invention enables secured debug of an integrated circuit (300) which has a test operation mode and a secure mission operation mode. The integrated circuit has a processing unit (340), a test interface (312) through which the test operation mode is controllable, an on-chip memory (350) which is accessible in the test operation mode and in the secure mission operation mode, and one or more protected resources (360, 364, 370) which are inaccessible in the test operation mode. The processing unit is configured, in the test operation mode, to receive (401) an authenticated object (401) through the test interface, and store (401) the received authenticated object in the on-chip memory. The processing unit is moreover configured, upon reset into the secure mission operation mode, to execute a boot procedure (362) to determine (501) that the authenticated object is available in the on-chip memory, authenticate (502) the authenticated object, and - upon successful authentication - render (503a, 503b) the more protected resources accessible to a debug host (310) external to the integrated circuit.