发明公开
EP2887395A1 Nonvolatile latch circuit and logic circuit, and semiconductor device using the same
审中-公开
NichtflüchtigeSperrschaltung und Logikschaltung sowie Halbleiterbauelement damit
- 专利标题: Nonvolatile latch circuit and logic circuit, and semiconductor device using the same
- 专利标题(中): NichtflüchtigeSperrschaltung und Logikschaltung sowie Halbleiterbauelement damit
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申请号: EP15154322.0申请日: 2010-10-29
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公开(公告)号: EP2887395A1公开(公告)日: 2015-06-24
- 发明人: Kato, Kiyoshi , Koyama, Jun
- 申请人: Semiconductor Energy Laboratory Co., Ltd.
- 申请人地址: 398, Hase Atsugi-shi, Kanagawa 243-0036 JP
- 专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人: Semiconductor Energy Laboratory Co., Ltd.
- 当前专利权人地址: 398, Hase Atsugi-shi, Kanagawa 243-0036 JP
- 代理机构: Grünecker Patent- und Rechtsanwälte PartG mbB
- 优先权: JP2009265738 20091120
- 主分类号: H01L27/105
- IPC分类号: H01L27/105 ; H01L21/8234 ; H01L21/8242 ; H01L27/00 ; H01L27/088 ; H01L27/10 ; H01L27/108 ; H01L29/786 ; H03K3/037 ; H03K3/356 ; H03K19/00 ; H03K19/0948 ; H03K19/096 ; G11C14/00 ; G11C7/04 ; G11C16/04 ; H01L21/02 ; H01L21/28 ; H01L29/66 ; H01L27/12 ; H03K3/286
摘要:
The invention provides a circuit comprising a first element; a second element; a first transistor; a second transistor; and a capacitor, wherein an output of the first element is electrically connected to an input of the second element, and an output of the second element is electrically connected to an input of the first element, wherein the input of the first element is electrically connected to a first wiring configured to be supplied with an input signal and the output of the first element is electrically connected to a second wiring configured to be supplied with an output signal, wherein a channel formation region of the first transistor includes an oxide semiconductor, wherein one of a source and a drain of the first transistor is electrically connected to the second wiring, wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor and a gate of the second transistor, and wherein one of a source and a drain of the second transistor is electrically connected to the first wiring.
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