发明公开
EP3061070A2 SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING 有权
于执行分级结构Z剔除部分覆盖瓦片选择性归并

  • 专利标题: SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING
  • 专利标题(中): 于执行分级结构Z剔除部分覆盖瓦片选择性归并
  • 申请号: EP14789461.2
    申请日: 2014-10-08
  • 公开(公告)号: EP3061070A2
    公开(公告)日: 2016-08-31
  • 发明人: WANG, TaoGRUBER, Andrew EvanKHANDELWAL, Shambhoo
  • 申请人: Qualcomm Incorporated
  • 申请人地址: International IP Administration 5775 Morehouse Drive San Diego, CA 92121-1714 US
  • 专利权人: Qualcomm Incorporated
  • 当前专利权人: Qualcomm Incorporated
  • 当前专利权人地址: International IP Administration 5775 Morehouse Drive San Diego, CA 92121-1714 US
  • 代理机构: Loveless, Ian Mark
  • 优先权: US201314061506 20131023
  • 国际公布: WO2015061044 20150430
  • 主分类号: G06T15/00
  • IPC分类号: G06T15/00 G06T15/40
SELECTIVELY MERGING PARTIALLY-COVERED TILES TO PERFORM HIERARCHICAL Z-CULLING
摘要:
This disclosure describes techniques for performing hierarchical z-culling in a graphics processing system. In some examples, the techniques may involve selectively merging partially-covered source tiles for a tile location into a fully-covered merged source tile based on whether conservative farthest z-values for the partially-covered source tiles are nearer than a culling z-value for the tile location, and using a conservative farthest z-value associated with the fully-covered merged source tile to update the culling z-value for the tile location. In further examples, the techniques may use a cache unit that is not associated with an underlying memory to store conservative farthest z-values and coverage masks for merged source tiles. The capacity of the cache unit may be smaller than the size of cache needed to store merged source tile data for all of the tile locations in a render target.
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