发明公开
EP3149943A1 CONTENT AWARE SCHEDULING IN A HEVC DECODER OPERATING ON A MULTI-CORE PROCESSOR PLATFORM
审中-公开
目录清醒规划方面取得HEVC解码器在多核心处理器平台OPERATED
- 专利标题: CONTENT AWARE SCHEDULING IN A HEVC DECODER OPERATING ON A MULTI-CORE PROCESSOR PLATFORM
- 专利标题(中): 目录清醒规划方面取得HEVC解码器在多核心处理器平台OPERATED
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申请号: EP15729985.0申请日: 2015-05-28
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公开(公告)号: EP3149943A1公开(公告)日: 2017-04-05
- 发明人: NELLORE, Anilkumar , PICHUMANI, Padmagowri , KULKARNI, Vinay , GUBBI, Chetan Kumar Viswanath , RAMAMURTHY, Shailesh , CHANDRASHEKAR, Padmassri
- 申请人: ARRIS Enterprises LLC
- 申请人地址: 3871 Lakefield Drive Suwanee, GA 30024 US
- 专利权人: ARRIS Enterprises LLC
- 当前专利权人: ARRIS Enterprises LLC
- 当前专利权人地址: 3871 Lakefield Drive Suwanee, GA 30024 US
- 代理机构: Openshaw & Co.
- 优先权: US201462003695P 20140528
- 国际公布: WO2015184067 20151203
- 主分类号: H04N19/13
- IPC分类号: H04N19/13 ; H04N19/186 ; H04N19/174 ; H04N19/17 ; H04N19/44 ; H04N19/82 ; H04N19/436
摘要:
A method is provided for decoding an encoded video stream on a processor having a plurality of processing cores includes receiving and examining a video stream to identify any macroscopic constructs present therein that support parallel processing. Decoding of the video stream is divided into a plurality of decoding functions. The plurality of decoding functions is scheduled for decoding the video stream in a dynamic manner based on availability of any macroscopic constructs that have been identified and then based on a number of bytes used to encode each block into which each picture of the video stream is partitioned. Each of the decoding functions is dispatched to the plurality of processing cores in accordance with the scheduling.
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