发明公开
EP3164887A1 STRUCTURE AND METHOD OF BATCH-PACKAGING LOW PIN COUNT EMBEDDED SEMICONDUCTOR CHIPS
审中-公开
结构与方法采用了低引脚的嵌入式半导体芯片的收集 - 包装
- 专利标题： STRUCTURE AND METHOD OF BATCH-PACKAGING LOW PIN COUNT EMBEDDED SEMICONDUCTOR CHIPS
- 专利标题（中）： 结构与方法采用了低引脚的嵌入式半导体芯片的收集 - 包装
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申请号： EP15815539.0申请日： 2015-07-01
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公开(公告)号： EP3164887A1公开(公告)日： 2017-05-10
- 发明人: MASUMOTO, Mutsumi
- 申请人： Texas Instruments Incorporated
- 申请人地址： P.O. Box 655474 Mail Station 3999 Dallas, TX 75265-5474 US
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： P.O. Box 655474 Mail Station 3999 Dallas, TX 75265-5474 US
- 代理机构： Zeller, Andreas
- 优先权： US201414320825 20140701
- 国际公布： WO2016004238 20160107
- 主分类号： H01L23/538
- IPC分类号： H01L23/538 ; H01L21/56
摘要：
A method for fabricating packaged semiconductor devices in panel format. A flat panel sheet dimensioned for a set of contiguous chips includes a stiff substrate of an insulating plate, and a tape having a surface layer of a first adhesive releasable at elevated temperatures, a core base film, and a bottom layer with a second adhesive attached to the substrate. Attaching a set onto the first adhesive layer, the chip terminals having terminals with metal bumps facing away from the first adhesive layer. Laminating low CTE insulating material to fill gaps between the bumps and to form an insulating frame surrounding the set. Grinding lamination material to expose the bumps. Plasma-cleaning assembly, sputtering uniform metal layer across assembly, optionally plating metal layer, and patterning metal layer to form rerouting traces and extended contact pads.
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