An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, wherein the interleaver circuit is configured to order parity bits such that odd parity bits precede even parity bits within each group of parity bits and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.