An embodiment of the present invention relates to a low-power broadband asynchronous BPSK demodulation method and a configuration of a circuit thereof. In connection with a configuration of a BPSK demodulation circuit, there may be provided a low-power wideband asynchronous binary phase shift keying demodulation circuit comprising: a sideband separation and lower sideband signal delay unit for separating a modulated signal into an upper sideband and a lower sideband using a primary high pass filter, which has a carrier frequency as the cutoff frequency thereof, and a primary low pass filter and digitalizing the same into a positive phase and a negative phase such that, in connection with a digital output from a lower sideband comparator and a digital output from an upper sideband comparator, signals with opposite phases are compared at the same ascending edge and at the same descending edge between a symbol edge and another symbol edge, respectively, thereby reducing jitter to the largest extent, improving the yield ratio, and outputting lower sideband digital signals and upper sideband digital signals, the lower sideband digital signals having been delayed by the 1/4 frequency of the carrier frequency; a data demodulation unit for generating a first symbol edge signal detected by aligning the phase difference between a delayed lower sideband positive-phase digital signal and an upper sideband negative-phase digital signal to be 180° and generating a second symbol edge signal detected by aligning the phase difference between a delayed lower sideband negative-phase digital signal and an upper sideband positive-phase digital signal to be 180°, the data demodulation unit overlapping the first symbol edge signal and the second symbol edge signal through an AND gate, thereby reducing the glitch and generating a symbol edge clock, which has no glitch, through a deglitch filter, the data demodulation unit synchronizing the delayed lower sideband positive-phase digital signal with a descending edge of the symbol edge signal, thereby demodulating data; and a data clock restoration unit for generating a data clock using the delayed lower sideband positive-phase digital signal and the demodulated data signal.