Cache logic for generating a cache address from a binary memory address comprising a first binary sequence of a first predefined length and a second binary sequence of a second predefined length, the cache logic comprising: a plurality of substitution units each configured to receive a respective allocation of bits of the first binary sequence and to replace its allocated bits with a corresponding substitute bit string selected in dependence on the received allocation of bits; a mapping unit configured to combine the substitute bit strings output by the substitution units so as to form one or more binary strings of the second predefined length; and combination logic arranged to combine the one or more binary strings with the second binary sequence by a reversible operation so as to form a binary output string for use as at least part of a cache address in a cache memory.