Systems and methods for optimizing a memory rail voltage are disclosed. The system may comprise a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage higher than a data retention voltage of a similar memory bit cell. The sensor cells may be configured to provide an output based on a sensor rail voltage higher than the predefined data retention voltage. The system may further comprise a controller operably coupled to a power management circuit and configured to adjust the memory rail and the sensor rail voltages. The controller may be further configured to compare an expected value to the sensor indication. The controller may decrease the sensor rail voltage and the memory rail voltage based on the indication until a sensor indicates a bitcell replica has failed, indicating an optimum memory rail voltage has been reached.