Invention Publication
- Patent Title: HARDWARE IMPLEMENTATION OF A TEMPORAL MEMORY SYSTEM
- Patent Title (中): 硬件实现时间存储系统
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Application No.: EP17181762.0Application Date: 2017-07-17
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Publication No.: EP3273390A3Publication Date: 2018-02-28
- Inventor: DEGRAEVE, Robin , RODOPOULOS, Dimitrios
- Applicant: IMEC vzw
- Applicant Address: Kapeldreef 75 3001 Leuven BE
- Assignee: IMEC vzw
- Current Assignee: IMEC vzw
- Current Assignee Address: Kapeldreef 75 3001 Leuven BE
- Agency: DenK iP
- Priority: EP16180038P 20160718
- Main IPC: G06N3/063
- IPC: G06N3/063 ; G06N3/04
Abstract:
A hardware implementation of a temporal memory system (10) comprises
- at least one array (360, 361, 362) of memory cells (40) logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing, e.g. for incrementing or decrementing, the stored scalar value,
- an input system (340) adapted for receiving an input frame as input and for creating a representation for that input, which is fit for memory cell addressing in the at least one array,
- at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, the at least one addressing unit comprising
- a column addressing unit (41) for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of cells, and
- a row addressing unit (42) for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells,
- a reading unit (43) adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, this likelihood being adjustable through the scalar value stored in the memory cell.
- at least one array (360, 361, 362) of memory cells (40) logically organized in rows and columns, each memory cell being adapted for storing a scalar value and adapted for changing, e.g. for incrementing or decrementing, the stored scalar value,
- an input system (340) adapted for receiving an input frame as input and for creating a representation for that input, which is fit for memory cell addressing in the at least one array,
- at least one addressing unit for identifying a memory cell in the at least one array with a row address and a column address, the at least one addressing unit comprising
- a column addressing unit (41) for receiving the representation or a derivative thereof as input and applying the representation or the derivative as a column address to the array of cells, and
- a row addressing unit (42) for receiving a delayed version of the representation at a specified time in the past as input, and applying this representation as a row address to the array of cells,
- a reading unit (43) adapted for reading out scalar values from a selected row of memory cells in the array, based on the row address applied, each read out scalar value corresponding to a likelihood of temporal coincidence between the input representation of the row address and the input representation of the column address, this likelihood being adjustable through the scalar value stored in the memory cell.
Public/Granted literature
- EP3273390B1 HARDWARE IMPLEMENTATION OF A TEMPORAL MEMORY SYSTEM Public/Granted day:2021-12-15
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