An array substrate includes a substrate having a display region and a peripheral region, at least one scan line, at least one data line, at least one pixel unit electrically connected to the scan line and the data line and disposed in the display region, and a gate driving circuit. The gate driving circuit is disposed in the peripheral region and includes multiple shift registers sequentially disposed on the substrate along a first direction. At least one shift register includes a pull-up unit, which includes a first transistor configured to output a gate signal to the scan line. The first transistor includes a first gate, a first channel layer, and a first source and a first drain which respectively have at least one bar portion. A first channel length is between two adjacent bar portions of the first source and the first drain, which extends along the first direction.