发明公开
EP3298730A1 BUSSYSTEM UND VERFAHREN ZUM ZUTEILEN VON ADRESSEN VON BUSTEILNEHMERN EINES BUSSYSTEMS
审中-公开
总线系统和用于分配总线系统的总线参与者的地址的方法
- 专利标题: BUSSYSTEM UND VERFAHREN ZUM ZUTEILEN VON ADRESSEN VON BUSTEILNEHMERN EINES BUSSYSTEMS
- 专利标题(英): EP3298730A1 - Bus system and method for assigning addresses of bus components of a bus system
- 专利标题(中): 总线系统和用于分配总线系统的总线参与者的地址的方法
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申请号: EP16724375.7申请日: 2016-05-18
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公开(公告)号: EP3298730A1公开(公告)日: 2018-03-28
- 发明人: WOLF, Sebastian
- 申请人: Weidmüller Interface GmbH & Co. KG
- 申请人地址: Klingenbergstrasse 16 32758 Detmold DE
- 专利权人: Weidmüller Interface GmbH & Co. KG
- 当前专利权人: Weidmüller Interface GmbH & Co. KG
- 当前专利权人地址: Klingenbergstrasse 16 32758 Detmold DE
- 代理机构: Kleine, Hubertus
- 优先权: DE102015107865 20150519
- 国际公布: WO2016184889 20161124
- 主分类号: H04L12/403
- IPC分类号: H04L12/403 ; H04L12/40 ; H04L29/12 ; G06F12/06
摘要:
The invention relates to a bus system comprising a bus master (10), at least two bus components (20, 20') and a bus (30) which connects the bus components (20, 20') to the bus master (10), wherein the bus (30) has at least one data line (32) and at least one power supply line (31), characterised in that the at least one data line (32) connects the bus master (10) to all bus components (20, 20'), and the at least one power supply line (31) connects the bus master (10) to a first bus component (20) and is looped through the first bus component (20) to a further bus component (20'), wherein inside a bus component (20, 20') at least one switching element (25) is connected into the power supply line. The invention further relates to a method for assigning addresses in a bus system of this type.
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