发明公开
- 专利标题: METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE, AND DISPLAY DEVICE
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申请号: EP16727927.2申请日: 2016-01-14
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公开(公告)号: EP3327763A1公开(公告)日: 2018-05-30
- 发明人: LIU, Zheng , KUO, Tsung Chieh , CHEN, Xi , ZHANG, Xiaoxiang , ZHANG, Zhichao , LIU, Mingxuan
- 申请人: BOE Technology Group Co., Ltd. , Beijing BOE Display Technology Co., Ltd.
- 申请人地址: No. 10 Jiuxianqiao Road Chaoyang District Beijing 100015 CN
- 专利权人: BOE Technology Group Co., Ltd.,Beijing BOE Display Technology Co., Ltd.
- 当前专利权人: BOE Technology Group Co., Ltd.,Beijing BOE Display Technology Co., Ltd.
- 当前专利权人地址: No. 10 Jiuxianqiao Road Chaoyang District Beijing 100015 CN
- 代理机构: Cohausz & Florack
- 优先权: CN201510424976 20150717
- 国际公布: WO2017012306 20170126
- 主分类号: H01L21/77
- IPC分类号: H01L21/77 ; H01L27/12
摘要:
The present invention provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing an array substrate comprises: forming a pattern comprising a pixel electrode and a pattern comprising a gate of a thin film transistor on a substrate; forming a gate insulating layer; forming a pattern comprising an active layer and a source and a drain, which are provided on the active layer, of the thin film transistor by a patterning process; forming a passivation layer; forming a pattern comprising a main via penetrating through the gate insulating layer and the passivation layer and a main-via extension portion under a portion of the drain by a patterning process, wherein the main via is connected to the main-via extension portion; removing a portion of the drain which protrudes above the main-via extension portion so as to form a pattern comprising a final via; and forming a pattern comprising a connection electrode and a common electrode, wherein the connection electrode electrically connects the drain to the pixel electrode through the final via.
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