- 专利标题: DIGITAL SIGNAL PROCESSING SCHEME FOR HIGH PERFORMANCE HFC DIGITAL RETURN PATH SYSTEM WITH BANDWIDTH CONSERVATION
-
申请号: EP17206902.3申请日: 2004-06-08
-
公开(公告)号: EP3331167A1公开(公告)日: 2018-06-06
- 发明人: ZHANG, Mao Zhu , HOWARD, Robert L
- 申请人: ARRIS Enterprises LLC
- 申请人地址: 3871 Lakefield Drive Suwanee, GA 30024 US
- 专利权人: ARRIS Enterprises LLC
- 当前专利权人: ARRIS Enterprises LLC
- 当前专利权人地址: 3871 Lakefield Drive Suwanee, GA 30024 US
- 代理机构: Boult Wade Tennant
- 优先权: US465326 20030618
- 主分类号: H03M7/50
- IPC分类号: H03M7/50 ; H03M7/00
摘要:
In a cable return path system, a method for performing digital companding adds a predetermined offset to the digital value to be companded, and employs a modified µ-law or a-law companding technique to obtain a reduced bit length digital value. One embodiment of this modified approach adds a predetermined offset (e.g., 129 for a 12-bit implementation) to the digital value before companding and then employs a two-bit chord and a 5-bit step for the 12-bit implementation. The end result is that the performance metrics are not significantly compromised by this bit reduction when compared to current transmission methods without this technique.
公开/授权文献
信息查询
IPC分类: