The present disclosure relates to a method implemented in an electronic device comprising at least two processor cores. In one embodiment, the method comprises varying a maximum number of processor cores used for operating the electronic device, amongst the processor cores, and/or an operating frequency of at least one of the processor cores according to a load of at least one of the processor cores.
The present disclosure also relates to corresponding electronic device, and corresponding System on Chip, electronic device, electronic assembly, computer readable program product and computer readable storage medium.