Invention Publication
- Patent Title: NEURAL NETWORK CIRCUIT DEVICE, NEURAL NETWORK, NEURAL NETWORK PROCESSING METHOD, AND NEURAL NETWORK EXECUTION PROGRAM
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Application No.: EP17875690.4Application Date: 2017-11-28
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Publication No.: EP3564865A1Publication Date: 2019-11-06
- Inventor: NAKAHARA Hiroki , YONEKAWA Haruyoshi
- Applicant: Tokyo Institute of Technology
- Applicant Address: 2-12-1, Ookayama Meguro-ku Tokyo 152-8550 JP
- Assignee: Tokyo Institute of Technology
- Current Assignee: Tokyo Institute of Technology
- Current Assignee Address: 2-12-1, Ookayama Meguro-ku Tokyo 152-8550 JP
- Agency: Dehns
- Priority: JP2016235383 20161202
- International Announcement: WO2018101275 20180607
- Main IPC: G06N3/063
- IPC: G06N3/063
Abstract:
A binarized neural network circuit (100) includes: an input part (101) configured to allow input of input values x1-xn (xi) (binary) and weights w1-wn (wi); an XNOR gate circuit (102) configured to receive the input values x1-xn and the weights w1-wn and take XNOR logic; a multibit bias W' input part (110) configured to allow input of a multibit bias W'; a sum circuit part (103) configured to sum each of XNOR logical values and the multibit bias W'; and an activation circuit part (120) configured to output only a sign bit of a multibit signal Y generated by using the sum.
Information query
