- 专利标题： NEURAL NETWORK CIRCUIT DEVICE, NEURAL NETWORK, NEURAL NETWORK PROCESSING METHOD, AND NEURAL NETWORK EXECUTION PROGRAM
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申请号： EP17875690.4申请日： 2017-11-28
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公开(公告)号： EP3564865A1公开(公告)日： 2019-11-06
- 发明人: NAKAHARA Hiroki , YONEKAWA Haruyoshi
- 申请人： Tokyo Institute of Technology
- 申请人地址： 2-12-1, Ookayama Meguro-ku Tokyo 152-8550 JP
- 专利权人： Tokyo Institute of Technology
- 当前专利权人： Tokyo Institute of Technology
- 当前专利权人地址： 2-12-1, Ookayama Meguro-ku Tokyo 152-8550 JP
- 代理机构： Dehns
- 优先权： JP2016235383 20161202
- 国际公布： WO2018101275 20180607
- 主分类号： G06N3/063
- IPC分类号： G06N3/063
摘要：
A binarized neural network circuit (100) includes: an input part (101) configured to allow input of input values x1-xn (xi) (binary) and weights w1-wn (wi); an XNOR gate circuit (102) configured to receive the input values x1-xn and the weights w1-wn and take XNOR logic; a multibit bias W' input part (110) configured to allow input of a multibit bias W'; a sum circuit part (103) configured to sum each of XNOR logical values and the multibit bias W'; and an activation circuit part (120) configured to output only a sign bit of a multibit signal Y generated by using the sum.
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