An apparatus is described. The apparatus includes a semiconductor chip package. The semiconductor chip package includes an SOC. The SOC has a memory controller. The semiconductor chip package includes an interface to an external memory. The semiconductor chip package includes a memory side cache. The memory side cache is composed of eDRAM and is coupled between the memory controller and the interface to the external memory. The eDRAM is to cache more frequently used items of the external memory. The semiconductor chip package has an out-of-order interface between the memory controller and the memory side cache.