An all-digital phase locked loop (ADPLL) (10) is provided. The ADPLL (10) comprises a pattern generator (11) adapted to generate a frequency control word (FCW) (14) based on a predefined setting (12) and a system clock (13). In addition, the ADPLL (10) comprises a phase accumulator (15) adapted to translate the FCW (14) into a phase trajectory (16). The ADPLL (10) further comprises a phase comparator (17) adapted to generate a phase error signal (18) representing a difference between the phase trajectory (16) and the phase of an output oscillation frequency (25). Moreover, the ADPLL (10) comprises a control means (20) adapted to control a phase of the output oscillation frequency (25) with respect to the phase trajectory (16).