- 专利标题: APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS TO COMPARTMENTALIZE CODE
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申请号: EP20208101.4申请日: 2020-11-17
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公开(公告)号: EP3885901A1公开(公告)日: 2021-09-29
- 发明人: Sahita, Ravi , Gupta, Deepak , Shanbhogue, Vedvyas , Hansen, David , Brandt, Jason W. , Nuzman, Joseph , Zhang, Mingwei
- 申请人: Intel Corporation
- 申请人地址: US Santa Clara, CA 95054 2200 Mission College Boulevard
- 代理机构: Goddar, Heinz J.
- 优先权: US202016833478 20200327
- 主分类号: G06F9/30
- IPC分类号: G06F9/30 ; G06F9/355 ; G06F9/38 ; G06F12/02 ; G06F12/14
摘要:
Systems, methods, and apparatuses relating to instructions to compartmentalize memory accesses and execution (e.g., non-speculative and speculative) are described. In one embodiment, a compartment manager circuit is to determine, when a compartment control register of a hardware processor core is set to an enable value, that a first subset of code requested for execution on the hardware processor core in user privilege is within a first compartment of memory, load a first compartment descriptor for the first compartment into one or more registers of the hardware processor core from the memory, check if the first compartment is marked in the first compartment descriptor, within the one or more registers of the hardware processor core, as a management compartment, and, when the first compartment is marked in the first compartment descriptor as the management compartment, allowing the first subset of the code within the first compartment to load a second compartment descriptor for a second compartment of the memory into the one or more registers of the hardware processor core from the memory, switching execution from the first subset of code within the first compartment to a second subset of code in user privilege within the second compartment, allowing speculative memory accesses for the second subset of code only within the second compartment, and preventing a memory access outside of the second compartment for the second subset of code as indicated by the second compartment descriptor stored within the one or more registers of the hardware processor core.
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