This application provides a chip stacking package and a terminal device, and relates to the field of semiconductor technologies. The chip stacking package can resolve a problem of high costs caused by using a through silicon via technology while ensuring a power supply requirement. The chip stacking package (01) includes a first chip (101) and a second chip (102) disposed between a first routing structure (10) and a second routing structure (20). An active surface (S1) of the first chip (101) faces an active surface (S2) of the second chip (102). The active surface (S1) of the first chip (101) includes a first overlapping region (A1) and a first non-overlapping region (C1). The active surface (S2) of the second chip (102) includes a second overlapping region (A2) and a second non-overlapping (C2) region. The first overlapping region (A1) overlaps the second overlapping region (A2), and the first overlapping region (A1) is connected to the second overlapping region (A2). The first non-overlapping region (C1) is connected to the second routing structure (20). The second non-overlapping region (C2) is connected to the first routing structure (10).