Method and integrated circuit for indicating a failure of a critical path. The integrated circuit comprising: 1) a critical data path including a flip flop configured to receive a data input and provide a latched data output; and 2) a monitoring circuit including a delay generator configured to receive the data input and provide a plurality of delayed data outputs corresponding to delayed versions of the data input with increasing amounts of delay, a selector circuit configured to select one of the plurality of delayed outputs based on a programmable control value, a shadow latch coupled to an output of the selector circuit and configured to latch a value at its input to provide as a latched shadow output, a comparator circuit configured to provide a match error indicator based on a comparison between the first latched data output and the latched shadow output, a metastability detection circuit, and an error indicator configured to indicate a failure of the critical data path.