- 专利标题: VERTICAL BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING
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申请号: EP22205699.6申请日: 2022-11-07
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公开(公告)号: EP4235796A1公开(公告)日: 2023-08-30
- 发明人: MC TAGGART, Sarah A. , KRISHNASAMY, Rajendran , LIU, Qizhi
- 申请人: GlobalFoundries U.S. Inc.
- 申请人地址: US Malta, NY 12020 400 Stonebreak Road Extension
- 代理机构: Grünecker Patent- und Rechtsanwälte PartG mbB
- 优先权: US202217679166 20220224
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L29/08 ; H01L29/66 ; H01L29/732
摘要:
A semiconductor structure comprising: a dielectric layer (162); an emitter region (140) comprising: a first emitter portion (141) extending through the dielectric layer (162); and a second emitter portion (142) on the first emitter portion and further extending laterally onto the dielectric layer (162); and an additional dielectric layer (163) on the second emitter portion, wherein the dielectric layer (162), the second emitter portion (142), and the additional dielectric layer (163) are wider than the first emitter portion (141), and wherein at least a section of the second emitter portion (142) is narrower than the dielectric layer (162) and the additional dielectric layer (163). Preferably, the second emitter portion (142) increases in width between the dielectric layer (162) and the additional dielectric layer (163)
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