Systems, methods, and apparatuses relating to 8-bit floating-point matrix dot product instructions are described. For example, a processor comprises: a plurality of vector registers to store a plurality of packed data elements including 8-bit floating point data elements and 32-bit floating point data elements; decode circuitry to decode a single matrix multiplication instruction having fields to indicate an opcode and locations of an M by K first source matrix including a first plurality of the 8-bit floating point data elements, a K by N second source matrix including a second plurality of the 8-bit floating point data elements, and an M by N third source matrix having a plurality of 32-bit floating point data elements, each of the first and second plurality of 8-bit floating point data elements comprising a sign bit, a 5-bit exponent value, and a 2-bit mantissa value; and execution circuitry comprising matrix acceleration circuitry to accelerate matrix operations, wherein responsive to the single matrix multiplication instruction, the execution circuitry is to generate each 32-bit floating point result data element of a result matrix based on a corresponding row of the first plurality of 8-bit floating point data elements and a corresponding column of the second plurality of 8-bit floating point data elements, the execution circuitry to generate a respective plurality of products corresponding to the corresponding row of the first plurality of 8-bit floating point data elements and the corresponding column of the second plurality of 8-bit floating point data elements and to accumulate the plurality of products with a corresponding 32-bit floating point data element of the third source matrix to generate the 32-bit floating point result data element of the result matrix.