There is provided a memory controller 309 including an interface 301 and a processor. The processor fetches a memory request C1 in one of a plurality of queues Q1-Q4 storing a plurality of memory requests C1-C4 from a host 310, compares a destination address of the memory request C1 with a first stored destination address, among one or more stored destination addresses in a storage, associates the memory request C1 with the first stored destination address in the storage based on a match between the destination address of the memory request C1 and the first stored destination address in the storage, and processes one or more entries in the storage in response to the memory request C1.