Invention Patent
- Patent Title: Three dimensional ic method and device
- Patent Title (中): 三维IC方法和装置
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Application No.: JP2012246660Application Date: 2012-11-08
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Publication No.: JP2013058781APublication Date: 2013-03-28
- Inventor: PAUL M ENGQUIST , GAIUS GILLMAN FOUNTAIN JR , TONG QIN-YI
- Applicant: Ziptronix Inc , ジプトロニクス・インコーポレイテッド
- Assignee: Ziptronix Inc,ジプトロニクス・インコーポレイテッド
- Current Assignee: Ziptronix Inc,ジプトロニクス・インコーポレイテッド
- Priority: US20132105 2005-08-11
- Main IPC: H01L27/00
- IPC: H01L27/00 ; H01L21/3205 ; H01L21/768 ; H01L23/522 ; H01L25/065 ; H01L25/07 ; H01L25/18
Abstract:
PROBLEM TO BE SOLVED: To provide a method of three-dimensionally integrating elements such as singulated dies or wafers and an integrated structure having connected elements such as singulated dies or wafers.SOLUTION: Either or both of the die and wafer have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. The first and second contact structures can be exposed at bonding and is electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnect the first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, the first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect the first and second contact structures and provide electrical access to the interconnected first and second contact structures.
Public/Granted literature
- JP6195704B2 3DIC方法および装置 Public/Granted day:2017-09-13
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