Invention Patent
- Patent Title: Electronic component packaging method and electronic component packaging line
- Patent Title (中): 电子元件包装方法和电子元件包装线
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Application No.: JP2012012961Application Date: 2012-01-25
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Publication No.: JP2013153048APublication Date: 2013-08-08
- Inventor: SAEKI TSUBASA , MOTOMURA KOJI , MARUO HIROKI
- Applicant: Panasonic Corp , パナソニック株式会社
- Assignee: Panasonic Corp,パナソニック株式会社
- Current Assignee: Panasonic Corp,パナソニック株式会社
- Priority: JP2012012961 2012-01-25
- Main IPC: H05K3/34
- IPC: H05K3/34 ; H01L21/56 ; H01L21/60 ; H05K13/04
Abstract:
PROBLEM TO BE SOLVED: To provide a packaging method and a packaging line of an electronic component which improve preservative quality of flux and a reinforcement resin and ensures reliability of a solder joint part.SOLUTION: In an electronic component packaging method, an electronic component having multiple solder bumps is mounted on a substrate having a mounting region where multiple corresponding lands are provided. The electronic component packaging method includes the steps of: applying a thermosetting resin having first viscosity C1 to a reinforcement position set in a peripheral part of the mounting region so that the thermosetting resin contacts a peripheral part of the electronic component when the electronic component is mounted; applying flux, having second viscosity C2 that satisfies C1≤C2, to the multiple solder bumps; mounting the electronic component on the substrate so that the bumps, to which the flux is applied, are landed on the lands; and heating the substrate, on which the electronic component is mounted, to melt the bumps and hardening and cooling the thermosetting resin to join the electronic component to the substrate.
Public/Granted literature
- JP6135892B2 電子部品実装方法および電子部品実装ライン Public/Granted day:2017-05-31
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