Invention Patent
- Patent Title: A semiconductor die having a fine pitch electrical interconnection member
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Application No.: JP2013533871Application Date: 2011-09-26
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Publication No.: JP2013539925APublication Date: 2013-10-28
- Inventor: バリー,キース・レイク , パングル,シュゼット・ケイ , ビリャビセンシオ,グラント , リール,ジェフリー・エス
- Applicant: インヴェンサス・コーポレイション
- Assignee: インヴェンサス・コーポレイション
- Current Assignee: インヴェンサス・コーポレイション
- Priority: US201113243877 2011-09-23; US39331110 2010-10-14
- Main IPC: H01L21/60
- IPC: H01L21/60 ; H01L25/065 ; H01L25/07 ; H01L25/18
Abstract:
A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coating. Because the traces have a high interface angle, a tendency for the interconnect materials to bleed laterally is mitigated and contact or overlap of adjacent traces is avoided. The interconnect trace includes a curable electrically conductive interconnect material; that is, it includes a material that can be applied in a flowable form, and thereafter cured or allowed to cure to form the conductive traces. Also, a method includes, prior to forming the traces, subjecting the surface of the conformal dielectric coating with a CF4 plasma treatment.
Public/Granted literature
- JP5770852B2 ファインピッチ電気相互接続体を有する半導体ダイ Public/Granted day:2015-08-26
Information query
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