The 3D semiconductor memory device according to an embodiment of the present invention includes a first substrate including a first peripheral circuit region and a second peripheral circuit region, first transistors on the first peripheral circuit region of the first substrate, and the first substrate. 1 An interlayer insulating layer covering the first transistors on a substrate, first contact plugs connected to the first transistors and passing through the interlayer insulating layer, first contact wirings on the first contact plugs, and on the interlayer insulating layer A second substrate disposed on and including a first region and a second region, the first region overlapping the first peripheral circuit region, the second region overlapping the second peripheral circuit region, and the second substrate 2 It is disposed between the substrate and the interlayer insulating layer, and includes gate electrodes stacked on the second region of the second substrate and vertical channel portions passing through the gate electrodes, wherein the adjacent first contact wirings are capacitors It can be composed of electrodes of.