一种芯片封装结构的制程如下所述。首先,提供一具有多个第一开口的图案化导电层与一配置于其上的第一图案化防焊层。接着,形成一第二图案化防焊层于图案化导电层上,以使第一与第二图案化防焊层分别配置于图案化导电层的相对二表面上。然后,接合多个芯片至第一图案化防焊层上。之后,借由多条导线电性连接芯片至图案化导电层,其中导线贯穿图案化导电层的第一开口。接着,形成至少一封装胶体。然后,分割封装胶体、第一与第二图案化防焊层。

A manufacturing process for a chip package structure is described as follows. First, a patterned conductive layer having a plurality of first openings and a first patterned solder resist layer on the patterned conductive layer are provided. A second patterned solder resist layer is formed on the patterned conductive layer such that the first patterned solder resist layer and the second patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. Chips are bonded onto the first patterned solder resist layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings. At least one molding compound is formed and the molding compound, the first patterned solder resist layer and the second patterned solder resist layer are separated.