本发明系关于一种微电子封装,其具有:一微电子组件110,其上覆或黏着至一基板100之一第一表面102;及实质上硬质导电支柱106,其突出超过该第一表面或突出超过该基板之一远离该第一表面的第二表面104。曝露于该基板之与该等导电支柱突出超过之该表面相反的一表面处的导电组件108与该微电子组件电互连。一囊封物130上覆该微电子组件110之至少一部分及该等导电支柱106突出超过的该基板100之该表面102,该囊封物具有一凹座336或一或多个开口136、236,每一开口准许进行至至少一导电支柱之至少一电连接。至少一些导电支柱106彼此电绝缘且经调适以同时携载不同电位。在特定实施例中,该囊封物130中之该等开口136、140、146、236至少部分地曝露接合至支柱之导电块144,完全地曝露支柱106之顶表面126且部分地曝露支柱之边缘表面138,或可仅部分地曝露支柱之顶表面126。

A microelectronic package has a microelectronic element 110 overlying or mounted to a first surface 102 of a substrate 100 and substantially rigid conductive posts 106 projecting above the first surface or projecting above a second surface 104 of the substrate remote therefrom. Conductive elements 108 exposed at a surface of the substrate opposite the surface above which the conductive posts project are electrically interconnected with the microelectronic element. An encapsulant 130 overlies at least a portion of the microelectronic element 110 and the surface 102 of the substrate 100 above which the conductive posts 106 project, the encapsulant having a recess 336 or one or more openings 136, 236 each permitting at least one electrical connection to be made to at least one conductive post. At least some conductive posts 106 are electrically insulated from one another and adapted to simultaneously carry different electric potentials. In particular embodiments, the openings 136, 140, 146, 236 in the encapsulant 130 at least partially expose conductive masses 144 joined to posts, fully expose top surfaces 126 of posts 106 and partially expose edge surfaces 138 of posts, or may only partially expose top surfaces 126 of posts.