本发明提供一种芯片的叠层封装结构以及叠层封装方法，在所述叠层封装结构中，在进行第一层管芯封装时通过互连体和第一重布线体将电极引出，适应于焊盘间距密度较高的芯片封装，同时无需用到键合引线，减少了封装电阻，此外，利用贯穿第一包封体和基板的贯穿体引出第二层芯片上的电极，从而实现了芯片的叠层封装，有效的减少了集成电路的封装面积以及引脚数量。

The invention provides a package-on-package structure of a chip and a package-on-package method. In the package-on-package structure, an electrode is leaded out through an interconnector and a first rewiring member in packaging a first layer of pipe cores. The package-on-package structure and the package-on-package method are suitable for packaging the chip with relatively high pad spacing. Furthermore no bonding lead is required and a packaging resistance is reduced. Furthermore a penetrating member which penetrates a first packaging member and a substrate is used for leading the electrode on a second layer of the chip out, thereby realizing chip packaging in a package-on-package manner, effectively reducing the packaging area of an integrated circuit and number of pins.