一种供嵌埋半导体芯片之电路板结构及其制法，该结构系包括：内核板，系具有一第一表面及第二表面，于该第一表面及第二表面分别具有第一线路层及第二线路层，且于该第一表面具有一芯片置放区；压合层，系形成于该内核板之第一、第二表面及第一、第二线路层表面，且该压合层中形成有至少一开口以露出该芯片置放区；第三及第四线路层，系分别形成于该内核板之第一及第二表面上的压合层表面，该第三及第四线路层分别具有复数第一及第二电性连接垫；第一绝缘保护层，系形成于该压合层、第三线路层表面，该第一绝缘保护层中具有一第一开口以露出该第三线路层中之第一电性连接垫及芯片置放区；以及第二绝缘保护层，系形成于该压合层、第四线路层表面，该第二绝缘保护层中具有复数第二开口以露出该第四线路层中之第二电性连接垫；该芯片置放区系供接置一半导体芯片，俾以降低封装之整体高度。

A semiconductor chip-embedded circuit board and a fabrication method thereof are provided, including: a core board having first and second surfaces with first and second circuit layers thereon respectively, the first surface having a chip-receiving area (CRA); a laminated layer formed on the first and second surfaces and formed with an opening for exposing the CRA; third and fourth circuit layers formed on the laminated layer, the third circuit layer having first and second conductive pads, the fourth circuit layer having third conductive pads; a first insulating protective layer formed on the third circuit layer and formed with a plurality of first openings for exposing the first conductive pads and the CRA and a plurality of second openings for exposing the second conductive pads; and a second insulating protective layer formed on the fourth circuit layer and formed with third openings for exposing the third conductive pads. Mounting a semiconductor chip on the CRA reduces package height.