Invention Grant
- Patent Title: Method for placing parallel multiplier
-
Application No.: US15068931Application Date: 2016-03-14
-
Publication No.: US10002219B2Publication Date: 2018-06-19
- Inventor: Sungmin Bae , Hyung-Ock Kim
- Applicant: SAMSUNG ELECTRONICS CO., LTD.
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Lee & Morse, P.C.
- Priority: KR10-2015-0041641 20150325; KR10-2015-0118175 20150821
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method for placing a parallel multiplier with a placement and routing tool includes receiving a datapath netlist about the parallel multiplier, extracting locations of primary input cells and primary output cells from the datapath netlist using a structure analysis module, mapping the primary input cells and the primary output cells on a specific array using the placement and routing tool, and arranging columns of the primary input cells and the primary output cells based on physical sizes of the primary input cells. The columns are arranged using the placement and routing tool. The size of the specific array is determined according to a number of the primary input cells.
Public/Granted literature
- US20160283614A1 METHOD FOR PLACING PARALLEL MULTIPLIER Public/Granted day:2016-09-29
Information query