Invention Grant
- Patent Title: Method for reducing core-to-core mismatches in SOC applications
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Application No.: US15606098Application Date: 2017-05-26
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Publication No.: US10002802B2Publication Date: 2018-06-19
- Inventor: Sheng-Tang Wang , Chia-Ming Chang , Shih-Che Lin , Chao-Jui Wang
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66

Abstract:
Methods for reducing core-to-core mismatch are provided. The method includes measuring gate lengths of a representative pattern of each core in a first lot of SOC products by a measurement apparatus. Each of the SOC products in the first lot includes more than two cores identical to each other. The method also includes determining a tuning amount according to the differences between the gate lengths of each core, and adjusting at least one mask for critical dimensions of gate length of each core in a second lot of SOC products respectively according to the tuning amounts.
Public/Granted literature
- US20170263509A1 METHOD FOR REDUCING CORE-TO-CORE MISMATCHES IN SOC APPLICATIONS Public/Granted day:2017-09-14
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